![]() ![]() Wire DrawArea = (CounterX<640) & (CounterY<480) Īnd generate some red, green and blue signals (8 bits each). ![]() reg CounterX // counts from 0 to 799Īlways posedge pixclk) CounterX =656) & (CounterX=490) & (CounterY<492) We use a couple of counters that go through an 800x525 pixel area. The scrambling and extra bits are needed by the HDMI receiver to properly synchronize to and acquire each lane (make sure to check the DVI and HDMI specifications for more details). ![]() HDMI requires that we scramble the data and add 2 bits per color lane, so we have 10 bits instead of 8 and the link ends up transporting 30 bits per pixel. Things are in fact just a bit more complicated. The other 3 pairs transmit the red, green and blue 8bit signals, so we get something like that. The FPGA has 4 TMDS differential pairs to drive.įirst, the TMDS clock is simply the pixel clock, so it runs at 25MHz. With that in mind, we need a 24.5MHz pixel clock to achieve 60 frames per seconds, but HDMI specifies a 25MHz minimum pixel clock, so that's we use (which gets us a 61Hz frame rate). Our 640x480 frame is actually sent as an 800x525 frame. That's 307200 pixels per frame, and since each pixel has 24 bits (8 bits for red, green and blue), at 60Hz, the HDMI link transports 0.44Gbps of "useful" data.īut video signals usually also have an "off-screen" area, which is used by the HDMI receiver (TV or monitor) for some housekeeping. Let's create a 640x480 RGB 24bpp 60Hz video signal. we use 8 FPGA pins configured as 4 differential TMDS outputs. Our connection from an FPGA to an HDMI connector can hardly be simpler. Out of the 19 pins, 8 are of particular interest as they form 4 TMDS differential pairs to transport the actual high-speed video info. HDMI is a digital video interface, so is easy to drive from modern FPGAs. ![]()
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